TA700C

• 33.33 MHz clock with synchronous transfers
• peak transfer rate of 133 MB/s for 32-bit bus width (33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s)
• peak transfer rate of 266 MB/s for 64-bit bus width
• 32-bit or 64-bit bus width
• 32-bit address space (4 gigabytes)
• 32-bit I/O port space
• 256-byte configuration space
• 5-volt signaling

The TA700-C series Compact PCI/PCI-X Bus Analyzer Supports PCI up to operates from 66 MHz/64-bit & PCI-X up to 100 MHz (analyze) and 66MHz (exercise) with supports 3.3V and 5V signaling environments. Like LeCroy’s other PCI / PCI-X solutions, the TA700-C Series is loaded with features designed to quickly isolate issues and confirm proper device and system operation. In the analyzer mode, the TA Series passively monitors all bus activity and provides a deep array of features for precise control of filter/trigger functions as well as configurable display options. Many common PCI triggers are pre-defined for the user providing a one-touch selection for detection of protocol errors, specific address and data patterns, individual bus signals, hang conditions, burst activity, and other events. Pre-capture filtering allows the user to exclude idles, wait states, retries or specific address ranges from the buffer.

With the exerciser option, the TA Series adds the ability to generate all PCI or PCI-X bus cycles as either master or target. Working interactively with the analyzer, the exerciser can be conditionally executed based on bus events detected by the analyzer. A range of error injection features are available, allowing the user to control transactions on the bus at the bit level, clock-by-clock. Other advanced exerciser features include arbitration override, whereby the exerciser assumes control of the bus regardless of arbiter authority, master abort override, whereby the exerciser will wait beyond specification requirements for a target response, control of wait states and idle states, loop and iterate functionality, compliance testing, and a wealth of convenient read/write utilities.

All TA Series products provide an automated PCI Compliance Test Suite, which is designed to help confirm a device's conformance to the PCI Specification. These tests are operated by the user through the GUI, and provide a pass/fail report to the user upon completion. Each test executed is saved in Catalyst's trace view, so the user can easily investigate failed tests in a familiar format. Well over 100 tests are available, for testing across several areas, including component configuration, device control, device status, base addresses, VGA devices, and general component protocol testing.

Most TA Series products provide two timing modes, including a detection utility to isolate setup & hold violations on the bus as well as an asynchronous high-speed capture feature. For detection of setup & hold violations, the TA Series provides an effective 100ps resolution to precisely characterize individual signal violations. A second setup & hold utility provides a one-click characterization of worst-case setup & hold characteristics across the entire bus. The asynchronous timing mode over-samples the bus at 1.5ns (664MHz), providing the user with the ability to debug general timing issues, such as race conditions.

The TA Series performance feature is a graphical analysis tool designed to characterize dozens of bus operational metrics instantly, and in real-time. Many pre-defined measurements are provided, or the user can easily create custom measurements, including various selections for chart displays (bar, line, pie, stacked, etc.). Selections are available to characterize the entire bus, or to select specific devices for characterization. Performance bottlenecks are quickly isolated. Bus utilization, target and master

The real-time performance analysis can also be operated in conjunction with the exerciser, allowing the user to characterize a design under precisely controlled conditions. For example, the exerciser may be used to loop through a script of read commands, while the performance analysis utility reports on average completion latency. Metrics include bus utilization, throughput, idle time, and other important characteristics.

The TA Series provides automatic protocol error detection capabilities for both PCI and PCI-X protocols. A total of over 100 protocol error trigger points are provided. As errors are detected, they are displayed in the capture, identified by error type, described in detail, and referenced to the specification. The exerciser can optionally be operated in conjunction with the protocol error detection, allowing the user to force conditions that may result in non-compliant bus activity.

All TA Series products provide a dual-mode GUI approach, offering the user a convenient choice of an easy-to-use interface, suitable for most common analysis and debug tasks, or an advanced mode, offering sophisticated and powerful features for tackling more complex issues. In the easy mode, ideal for most tasks, the analyzer, exerciser, performance, and timing mode functions are executed quickly and easily through very straightforward, easily understood menu selections. In the advanced mode, control of these same functions is expanded with powerful low-level control of all processes, including a user-programmable 32-level state sequencer for capture/trigger logic.