Summit T3-16 Analyzer

LeCroy offers three protocol analyzer product lines (Summit™ , PETracer™ ML, Edge T1-4). The Summit T3-16 Analyzer is LeCroy's fifth generation architecture and highest performance platform. It provides full bidirectional support of x16, x8, x4, x2, and x1 at data rates up to 8 GT/s.With 8 GB of trace memory, it offers enough capacity for analyzing and recording extensive PCI Express data streams. Supporting lane widths up to x4 at 2.5 GT/s, the PETracer ML Analyzer has 2 GB of trace memory and offers outstanding performance for Gen1 PCI Express applications. For portability and ease-of-use the Edge T1-4 Analyzer offers Gen1 analysis and low cost form factor for add-in-boards applications

LeCroy offers three protocol analyzer product lines (Summit™ , PETracer™ ML, Edge T1-4). The Summit T2-16 Analyzer is LeCroy's fourth generation architecture and highest performance platform. It provides full bidirectional support of x16, x8, x4, x2, and x1 at data rates up to 5 GT/s.With 8 GB of trace memory, it offers enough capacity for analyzing and recording extensive PCI Express data streams. Supporting lane widths up to x4 at 2.5 GT/s, the PETracer ML Analyzer has 2 GB of trace memory and offers outstanding performance for Gen1 PCI Express applications. For portability and ease-of-use the Edge T1-4 Analyzer offers Gen1 analysis and low cost form factor for add-in-boards applications

LeCroy's PCI Express Protocol Analyzer solutions employ high impedance, non-intrusive probing technology thereby allowing fully unaltered data pass-through. In addition, it leverages the intuitive and powerful LeCroy Trace expert software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies and presents this knowledge to the user in a colorful, intuitive and easy to use graphical display, allowing users to quickly capture and validate PCI Express product designs. These analyzers enable IP, semiconductor, switch, software and system developers as well as add-on card vendors to quickly identify protocol violations and ultimately reduce development and debugging time.

Developers can use LeCroy's PCI Express Protocol solutions to easily capture and decode PCI Express Transaction Layer Packets (TLPs), Data Link Layer Packets (DLLPs), and low-level link traffic, including Training Sequences and Skip Ordered-sets. Some of the errors detected include: 8b/10b errors, such as invalid symbols and incorrect running disparity; CRC errors; idle data errors; and EDB (End-of-Packet Bad) errors. They also provide a detailed display of split transactions, correlating requests transmitted from one PCI Express endpoint with completions received from the endpoint at the opposite end of the link.

The PCI Express exercisers assist with generating PCI Express transactions, observing behavior, and performing both stress testing and compliance testing. The Summit Z3-16 supports the new Specification 3.0 ("Gen3") data rates of 8 GT/s across up to 16 lanes. The PETrainer ML Exerciser supports up to x4 lane widths at data rates of 2.5 GT/s. As complete solutions, both the Summit T3-16 and Summit Z3-16, or PETracer/Trainer™ systems give you the unique ability to record (capture) live traffic, modify the traffic, and then playback the exact data stream, or "script," using the exerciser.

LeCroy offers an integrated and automated compliance testing system, including the Protocol Test Card, approved by the PCI-SIG® as a standard tool for compliance testing for developers working with the new Gen2 specification.

The LeCroy SDA 6020 Analyzer and PCI Express Compliance and Development software offer a complete test and debug. QPHY-PCIe provides a highly automated solution for PCI Express 1.1.

The LeCroy SDA 13000 can perform PCI Express 2.0 Compliance Test and Debug. It can acquire and quickly analyze PCI Express 2.0 signals using the SigTest(PCI-SIG Compliance Utility). The SDA 13000 has the memory depth to acquire all required 1 million UI in a single acquisition. Waveforms can be saved in the TRC format and quickly analyzed by SigTest. Built into the standard SDA tools are the 14 Masks, 3 PLLs and 2 Jitter Filters specified by PCI-SIG.

Peripheral Component Interconnect Express(PCIe) protocol was developed by Microsoft, Dell, IBM, Intel, and others in 2002. It was first called 3GIO but later became known as PCI Express. The PCI Express architecture is a state-of-the-art serial interconnect technology that keeps pace with recent advances in processor and memory subsystems. From its initial release at 0.8V, 2.5GT/s(Giga Transfers), to the newly announced Gen3 at 8GT/s the PCI Express technology roadmap will continue to evolve, while maintaining backward compatibility, well into the next decade with enhancements to its protocol, signaling, electromechanical and other specifications. The PCI Express architecture retains the PCI usage model and software interfaces for investment protection and smooth development migration. The technology is aimed at multiple market segments in the computing and communication industries, and supports chip-to-chip, board-to-board and adapter solutions at an equivalent or lower cost structure than existing PCI designs. PCI Express 2.0 currently runs at 5GT/s or 500MBps per lane in each direction, providing a total bandwidth of 16GBps in a 16-lane configuration which is the largest size in use.

PCI Express Gen3 will run at 8GT/s but will use a different encoding system to double the data rate but keep power consumption as low as possible.

The PCI bus is aging. Continued emergence of faster CPU and memory speeds, high-performance graphics, gigabit networking and other applications requiring higher bandwidth have made this once proud I/O the bottleneck. PCI simply cannot keep up with these faster applications. In addition, today's internal systems are composed of numerous and sometimes proprietary interconnects, thus making it difficult for multiple internal and external systems to have a unified I/O.

PCI Express is ready to meet the challenges of new and emerging applications for the next decade. It is designed to tie together many different chip-level I/O components within PC systems and to partition the system by providing very high-speed interconnections between different functional units - which will enable radical new designs.

The PCI Express architecture is a general-purpose I/O interconnect that can scale across multiple market segments in both the computing and communications industries. It is designed to provide connectivity as a chip-to-chip interconnect, I/O interconnect for adapter cards, an I/O attach point to other interconnects such as 1394b, USB2.0, InfiniBand and Ethernet and as a graphics I/O attach point for increased graphics bandwidth.

• Scalable performance, achieved through wider link widths (x1, x2, x4, x8, x16, x32)
• Advanced power management
• Compatible with existing PCI OS's and software drivers
• Data integrity and error handling
• Support for real-time data traffic
• Support for multiple connection types such as chip-to-chip and board-to-board connectors

A PCI Express Link is composed of two low-voltage differential pairs; a dual simplex connection between A and B devices. Data transmission between A and B are run simultaneously in both directions. Links cannot be configured asymmetrically, with more lanes in one direction versus the other.

PCI Express is intended to support multiple connection types, including chip-to-chip connectors on a system board; board-to-board connectors such as PCI add-in card interconnects today; docking stations for mobile platforms; as well as new form factors yet to be developed. This flexibility will allow for innovative and radical designs in platforms for years to come.

Using a PCIE Protocol Analyzer from LeCroy allows developers to see PCIe transactions from the low level wire up through to the upper PCIe protocol layers. From this diagram a bit stream is extracted to a packet. Packets are extracted into one or more transactions. Transactions may be further integrated into higher level transfers. Looking at data this way allows better understanding of how well the protocol has been implemented and is performing.

• PCI-SIGhttp://www.pcisig.com/home
• Intel Developer Network for PCI Express http://developer.intel.com/technology/pciexpress/devnet/

The Summit T3-16 is LeCroy's fifth generation of protocol analyzers targeted at high speed PCI Express I/O-based applications such as workstation, desktop, graphics, storage, and network card applications.

	Title	Time
	Summit T3-16 PCI Express Protocol Analyzer Introduction Video	4:05

PCIe 3.0 technology achieves twice the effective data throughput rate of the PCIe 2.0 standard through a combination of increased data bit rate (5 GT/s moving to 8 GT/s) and the elimination of 8b/10b data encoding, which previously added an overhead of 20 percent to all data transfers. In eliminating 8b10b encoding, PCIe 3.0 technology now relies on the existing data scrambling techniques similar to those used for PCIe 2.0 technology to ensure that receivers maintain lock on the incoming data stream.

With advanced features such as support for PCI Express Spec 3.0, data rates of 2.5, 5 and 8 GT/s, lane widths from x1 to x16, and a full 8 GB of trace memory, the Summit T3-16 provides unmatched capability and flexibility for developers and users of advanced PCI Express products. The Summit T3-16 is by far the most advanced and sophisticated PCI Express Analyzer available in the market today.

As with other LeCroy PCI Express analyzers, the Summit T3-16 leverages the intuitive and powerful CATC Trace analysis software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies. The colorful, intuitive and easy to use graphical display allows you to quickly capture and validate PCI Express product designs. All LeCroy PCI Express protocol analyzers employ high-impedance, non-intrusive probing technology, thereby allowing fully unaltered data pass-through.

In addition to a full suite of advanced hardware and software features, the Summit T3-16 provides user-convenience and analysis features, such as support for "lane swizzling" which allows a board developer to lay out a Mid-Bus probe pad with lanes in non-standard order, simplifying the design of the board. Internally the Summit T3-16 maps the lanes back into their correct order and accurately displays the embedded bus traffic. Other software features include enhanced error checking for automatic identification of additional error types, more compact trace files that allow for faster analysis of trace data, and the choice of simplified or advanced modes for setting up trace recording options.

A new raw recording mode, Bit Tracer, allows bytes to be recorded as they come across the link, allowing debugging of PHY layer problems and combining the features of a logic analyzer format with a protocol analyzer format. The new auto sense link feature monitors negotiation between devices of different lane widths, and the bifurcated link support recombines multilink PCI Express operations that have been separated into narrower links.

The Summit T3-16 also supports Ethernet LAN port as a standard feature. By connecting over a LAN, engineers can operate the system remotely (e.g., install the client software on their desktop systems, and control an analyzer operating in a remote lab). Also, multiple engineers working collaboratively can time-share use of a single analyzer, reducing the need for an additional analyzer for each engineer, and increasing the cost effectiveness of the product.

The Summit T3-16 is available in two configurations—that support either x1, x2, x4, and x8; or x1, x2, x4, x8, and x16—to match user requirements with available budgets. The upward compatibility and 13 month warranty of the Summit T3-16 also provide investment protection for current Gen1 and Gen2 users who plan to upgrade to Gen3 devices in the future.

By leveraging years of experience in protocol analysis tools for emerging markets, LeCroy's PCI Express protocol analyzers blend sophisticated functionality with practical features to speed the development of PCI Express IP cores, semiconductors, graphics, servers, workstations, bridges, and switches.

• Powerful & Intuitive CATC Trace - Faster interpretation and debug of PCI Express traffic.



• Expert Software Extensive Decoding - Understand the protocol completely with accurate and reliable decoding of TLPs (Transaction Layer Packets) and DLLPs (Data Link Layer Packets) and all Primitives for PCI Express.
• LTSSM Flow Graph - Look at the trace from the LTSSM State machine perspective to understand how the link is behaving. Quickly see if states are getting stuck or if the link is going up or down. Navigate the trace using the state bubbles that are hyper linked to the trace.



• Compact Trace View - Compact the trace to get a better overall understanding of what is happening in the entire trace.

• Advanced Triggering/Filtering - Find Errors fast by isolating important traffic, specific errors or data patterns. Understand transactions more clearly by removing non-essential fields from the trace.



• Flow Control View - Check on credit behavior between Root complex and endpoint transactions. See the credit decrement and credit updates in the trace with clarity.



• Intelligent Reporting - Quickly identify and track error rates, abnormal link or timing conditions, display configuration space, and protocol specification details.



• One Button Error Report - View the entire trace for PCI Express Errors. Navigate to each error by clicking on the error indicated.



• Dword to Transaction Level Viewer - See and understand Symbol, Packet, Link and Split Transaction levels of the PCI Express protocol.



• Monitoring and Link Utilization - Troubleshoot throughput, link utilization, and bandwidth issues.



• BitTracer Software Option - Records the bytes as they come across the link. Allows debugging of PHY layer problems. Gives protocol analyzer the best of both worlds; a logic analyzer format and decoded protocol analyzer format.
• Auto Sense Link - Analyzes all traffic negotiation between two devices of different lane widths.



• SRIOV Decode Support - Analyze Single Root IO Virtualization enabled devices.



• MRIOV Decode Support - Analyze Multi Root IO Virtualization enabled devices.



• Lane Swizzling - Accommodates specialized or unique board layouts for MidBus connections.
• Deep Buffer Recording Capacity - Capture long recording sessions for analysis and problem solving up to 8 GB (4 GB in each direction).
• CRC Checking - Know that info being displayed is accurate.
• High-speed Interface Ports - No complicated setup required, with 1 Gb/s Ethernet and USB 2.0 ports available.
• Downloadable Trace Viewer - Share and annotate trace recordings within a development team.
• 13 Month Warranty - Protect your investment.