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1875A 15-BIT, HIGH RESOLUTION TIME-TO-DIGITAL CONVERTER

FOR TIME-OF-FLIGHT MEASUREMENTS AND MUON SPECTROSCOPY


The FASTBUS Model 1875A1 features 64 channels of TDCs which operate in Common Start Mode. The 1875A offers a dynamic range of 15 bits in its 12-bit data by employing a bi-range transfer characteristic. This unit offers an extremely high sensitivity of up to 25 psec/count (200 psec on the associated high range) and is, therefore, ideal for measuring time intervals in nuclear, atomic, molecular and elementary particle physics time-of-flight experi ments. For applications where less stringent requirements are needed, the resolution can be set by jumpers to 50 or 100 psec (400 psec and 800 psec, respectively on the associated high ranges). The unit is delivered configured for 50 psec resolution.

Model 1875A employs a time-to-charge converter principle followed by a common, multiplexed charge ADC. Only "hit" channels are converted. The conversion time is 10 µsec + 2.5 µsec per hit channel. The module contains a multiple event buffer which can store up to 8 events. This buffer can be read out at up to 10 megawords/sec, concurrently with the conversion of following events, thus reducing dead time and simultaneously increasing signal throughput rate.

The 1875A is compatible with the LeCroy 1800 Series data acquisition modules and the LIFT software package.

FUNCTIONAL DESCRIPTION

Input Circuit

The 1875A input circuit uses time-to-charge converters to supply LeCroy Model MIQ401 4-Channel Charge Multiplexers with charge proportional to the time between Common Start and Stops. The MIQ401 is designed to do the integrate-and-store function as well as the output multiplexing to the common integrator & ADC.

In order to minimize turn-on effects of the charge storage circuitry, a minimum delay of 45 nsec between the Common Start and the first hit is required. The measurement window begins after this 45 nsec and ends one full scale later.

The Model 1875A Block Diagram

Conversion Technique

In order to cover a wide dynamic range with a single 12-bit ADC, the 1875A uses a dual range technique (see graph). This scheme allows less than 1% quantization error from 2.5 nsec to 800 nsec for the most sensitive range setting and produces 15 bits of dynamic range.

When set to the highest of three possible sensitivity settings, inputs < 100 nsec digitize with a resolution of 25 psec per count and signals between 100 nsec and 800 nsec digitize with a resolution of 200 psec per count. The digitized output from each channel that was hit consists of a 12-bit amplitude word and a range bit (13th bit). The user can select "low range", "high range" or "auto range" under program control. These numbers scale with the two other jumper-selectable resolution settings.

Dual Range Technique for Increased Dynamic Range Graph

Multiple Event Buffering

The module contains a multiple event buffer (digital memory) which can store up to eight events. Two pointers are used to allow the data acquisition program to follow the event flow.

Control

The 1875A may be used with the optional Model 1810 CAT module which provides the calibration and trigger signals required by the TDC. Operation without a CAT is also possible using the software-selectable, front-panel Common Start and Fast Clear Inputs. Modules may be read out using any FASTBUS Master such as a LeCroy Model 1821 FASTBUS Segment Manager/Interface (SM/I). In addition, the 1875A is compatible with the LIFT (LeCroy Interactive FASTBUS Toolkit) software package.

Self Test

The 1875A contains test circuits, allowing all TDC channels to be calibrated to approximately 3%. The calibration circuits are voltage-programmed pulse generators. A DC level (TEST REF) is bused from the LeCroy Model 1810 CAT module to all modules within the FASTBUS crate using the FASTBUS UR lines. When calibration is enabled via CSR 0, a write to CSR 0 <11> causes a Common Start-Stop pulse pair to deposit a well-defined charge (proportional to the TEST REF level) in each of the MIQ401 inputs.

1 The 1875A is a successor to the 1875. The major differences are the sparsified readout and the conversion from Common Stop operation in the 1875 to Common Start operation in the 1875A.

SPECIFICATIONS

GENERAL

Type: Time-to-charge converter feeding into a Common, multiplexed charge ADC.

Channels: 64. The number of active channels is programmable between 1 and 64 in steps of 1 channel.

Hit Inputs: 64, differential ECL. Impedance 112 ohm. Unused inputs are allowed to float. Minimum width: 10 nsec.

Signal Input Connector: 4, 34-pin headers on front panel.

Common Start: Differential ECL input via a 2-pin front-panel connector or via TR5 (B51) line on the FASTBUS backplane, or via CSR 0 <11>. Must proceed hits by 45 nsec. May be driven by the LeCroy Model 1810 CAT Module. Width: 50 nsec to 2 µsec.

Conversion in Progress (CIP): Front-panel output to indicate an A-to-D conversion of signals is occurring. ECL signal on 2-pin header.

Fast Clear: Differential ECL input via a 2-pin front-panel connector or via backplane TR0 line (jumper enabled). Minimum width 20 nsec. Clears module and readies it for acceptance of a new event. Fast clear settling time is < 950 nsec to < 0.1% of reading or 1 count, whichever is greater.

Full Scale: Jumper selectable. Low Range: 100/200/400 nsec; High Range: 800 nsec/1.6 µsec/3.2 µsec. Full scale always corresponds to 4095 counts.

Sensitivity (Resolution): Jumper selectable. Low range: 25/50/100 psec/count ±3%; high range: 200/400/800 psec/count ±5%.

Pedestal: (calibrated at the minimum encodable stop time input for the slowest channel on the unit, i.e., the enable time) 300 ±200 counts. Pedestal correction may take place during data readout by LeCroy Model 1821 Segment Manager/Interface.

Enable Time: < 45 nsec when measured from front panel Common Start connector to the slowest of the 64 stop inputs. Channel-to-channel enable time variation: < ±3 counts.

Integral Non-Linearity: < ±3 counts low range, <±6 counts high range.

Differential Non-Linearity: No missing codes guaranteed; ±0.25 LSB (For units manufactured after April 1995), worst case from 10 - 100% full scale beyond pedestal.

R.M.S. Noise: 1.0 count typical, 2 counts maximum.

Interchannel Isolation: 1.0 count typical, 2.5 counts maximum.

Temperature Coefficient: Gain is 80 ppm/°C; Pedestal is 0.3 counts/°C.

Long Term Stability: ±(0.25% of reading +10 counts)/w eek.

ADC: 12 bits (4096 counts).

Conversion Time: 2.5 µsec for each channel that is stopped ("hit") + 10 µsec.

Multiple Event Buffer: The digital data memory is large enough to store the results of up to 8 events. A 3-bit event counter allows the user to keep track of how many events the readout is trailing the conversion.

Measure Pause Interval Input: Single-ended ECL signal via TR5 (B51) line on FASTBUS backplane. May be driven by the Model 1810 CAT Module. Trailing edge defines when conversion starts, if enabled by program. Can last up to 300 µsec after a Stop signal.

Calibration Test Feature: Allows the gain of any channel to be measured to approximately 3% when using the LeCroy Model 1810 CAT Module.

Packaging: Single-width FASTBUS module in conformance with FASTBUS Specification (ANSI/IEEE-960) 1986.

Power Requirements: 3.4 A at +5.0 V, 5.0 A at -5.2 V, 2.0 A at -2.0 V, 0.6 A at +15 V, 0.3 A at -15 V.

CONTROL FUNCTIONS IMPLEMENTED (CSR SPACE)


Module ID: (1037)h.

Auto Range Select: Sets the readout conversion mode to Auto/Range.

Hi-Lo Range Select: Fixes the readout conversion mode to high or low range.

Start Source: Selects between front panel or the FASTBUS TR5 line as the source of the Common Start. Writing CSR0 <11> to produce a Common Start is always enabled.

Test Enable: Enables test mode.

Trigger Personality Programming: Addressing supplied for sixteen 8-bit user-supplied registers.

FASTBUS CONTROL


Implemented Addressing Modes: Geographical, Secondary, Broadcast.

Implemented Broadcast Functions:

01h - General Broadcast Select: Modules are selected and respond to subsequent data cycles.

09h - Sparse Data Scan (SDS): Modules containing data assert "T pin" on the following read data cycle.

09h - Pattern Select: Modules seeing their T pin asserted on the following write data cycle become selected to respond to subsequent data cycle.

ODh - All Device Scan: All modules assert their T pin on the following read data cycle.

DDh - TDC SDS: Unique Sparse Data Scan for 1870 Series modules only. Followsstandard SDS
(see above).

EDh - Personality Card Sparse Data Scan: SDS Module asserts T pin if Personality Card requires service.

An h subscript indicates hexadecimal (base 16).

FASTBUS REGISTER CONFIGURATIONS

CSR 0 Write Bit Definitions


CSR 0 Read Bit Definitions

After Power up or Reset
CSR 0 = 1037 3200h


CSR 1 Bit Definitions


DSR 0 Output Data Word Bit Definitions


l = bits which give module ID upon read but are also implemented for write operations.
i = bits which give module ID upon read and are not used for write operations.
* = unused bits which read back zero.
R = bits implemented for read operations only.
W = bits implemented for write operations only.
X = bits implemented for read and write operations.

Copyright© January 1996. LeCroy is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publicaction supersedes all earlier versions.