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1885F 15-BIT CHARGE ANALOG-TO-DIGITAL CONVERTER

FOR CALORIMETRY IN HEAVY ION AND PARTICLE PHYSICS


The FASTBUS Model 1885F contains 96 channels of analog-to-digital converter (ADC) with current integrating negative in puts. The 1885F offers the equivalent dynamic range of a 15-bit ADC in its 12-bit data using a bi-linear technique.

Gated integrating ADCs provide high flexibility. The use of gated integrators allows the shaping time of the system to be deter mined at run time. The same ADC can be used to encode photomultiplier and chamber signals or to sample slowly varying signals. DC-coupled gated integrators are best suited to high rate applications, especially when a wide dynamic range is re quired.

The maximum conversion time of the 1885F is 265 µsec. This ADC contains a multiple event buffer which can store up to 8 events. This buffer can be read out (at up to 10 megawords/sec) concurrently with the conversion of following events, substan tially reducing the dead time of the data acquisition system.

The 1885F may be used with the Model 1810 CAT module to provide the Calibration and Trigger signals required by the ADC. Operation without a CAT is also possible using the front-panel Gate and Fast Clear Inputs. Data readout is in accordance with the FASTBUS Standard (ANSI/IEEE-960). The modules may be read out via a LeCroy Model 1821 FASTBUS Segment Manager/Interface (SM/I).

The 96 inputs are expected via standard twisted-pair mass terminated cables. Paddle cards may be employed to ease the routing of the input cables as well as to adapt the signal levels or signal polarity to the requirements of the 1885F.

A 24-channel pre-amplifier card, Model 2724, with 15-bit dynamic range is available from LeCroy for applications requiring higher input sensitivity than the ADC module provides.

FUNCTIONAL DESCRIPTION

Input Circuit

The input circuit employs charge multiplexer, QMUX MIQ400 Series, monolithic circuits. The QMUX is designed to do an integrate-and-store function as well as multiplexing the output to a common amplifier and ADC.

Each input signal is split into three parts called "low range" (80% of the input signal), "high range" (10% of the input signal) and "current sum" (10% of the input signal). Note that the current sum is an ungated signal whereas the rest of the signals are gated.

Model 1885F Block Diagram

Conversion Technique

In order to cover a wide dynamic range with a single 12-bit ADC, the Model 1885F ADC uses a dual range technique. (See graph.) This scheme allows less than 1% quantization error from 5 pC to 1450 pC and corresponds to 15 bits of dynamic range.

For input less than 175 pC the 1885F ADC digitizes the signal with a resolution of 50 fC per count. For signals between 175 and 1450 pC the resolution is 400 fC/count. The digitized output from each channel consists of a 12-bit amplitude word and a range bit (13th bit). The user can select "low range", "high range" or "auto range" under program control.

Dual Range Technique for Increased Dynamic Range Graph

Multiple Event Buffering

The module contains a multiple event buffer (digital memory) which can store up to eight events. Two pointers are used to allow the data acquisition program to follow the event flow.

Calibration

The 1885F contains calibration circuits allowing the gain of all ADC channels to be measured to better than 1.5%. The calibration circuits are voltage-programmed pulse generators. A DC level (TEST REF) is bused from the 1810 CAT module to all modules within the FASTBUS crate using the FASTBUS UR lines. When the module is gated via CSR 0, the leading edge of the Gate causes a well defined charge (proportional to the TEST REF Level) to be deposited in each of the inputs.

Analog Output

Twenty-four sum output signals may be used for triggering. They are routed to the FASTBUS Auxiliary Connec tor. Each of these 24 signals is 10% of the ungated sum of a group of four adjacent channels. The output stages are open collectors, allowing further summing to be easily performed. The 1885F module also provides power and control at the Auxiliary Connector.

SPECIFICATIONS

GENERAL

ADC Type: Gated Current-Integrating, 12 bits.

Signal Inputs: 96 input channels. Quasi-differential. Impedance 50 ohm on each of the 2 input pins belonging to one channel; 100 ohm differential. Protected to ±100 V for 1 µsec.

Signal Input Connector: Six 34-pin headers on front panel.

Gate Input: Differential ECL input via a 2-pin front-panel connector or TR1 (B47) and TR2 (B48) lines on the FASTBUS backplane. May be driven by the Model 1810 CAT Module. The front-panel input uses removable termination resistors for busing of more than one module; 50 nsec to 2 µsec. (Guaranteed by design. Not tested.) Caution: at lower gate widths the peak signal currents may conflict with linearity and/or full scale specifications.

Common Mode Rejection Ratio: > 50 dB for ±200 mV DC to 1 kHz.(Guaranteed by design. Not tested.)

Conversion In Progress (CIP) Output: Front-panel output to indicate an A-to-D conversion is occurring. ECL signal on 2-pin header.

Fast Clear: Differential ECL input via a 2-pin front-panel connector or backplane T0 line. Clears module and readies it for a new Gate. For channel occupancy less than 50%, ADC results settle to within ±2 counts in less than 600 nsec. For higher occupancy, clearing time is 950 nsec.

Fast Analog Output: 24 ungated current sum signals on Auxiliary FASTBUS connector. Signal shape same as analog input; signal amplitude = 0.1 times input signal amplitude. Output impedance: 100 kohm. Output compli ance: 4 to 7 V.

Test Conditions for Following Specifications: (Unless otherwise stated.)

1. 25 pC input.
2. FASTBUS crate occupied by one Model 1821SM/I, one 1810 CAT and one unit under test.
3. 1.5 µsec gate width.
4. 10 µsec MPI.

Pedestal: 300 ±200 counts. Pedestal spread is reduced with narrower gates. Adjustable with an on-board trim pot.

Full Scale Charge: Low range, 170 pC1; high range 1350 pC. (Guaranteed by design. Not tested.)

Sensitivity: Low range, 50 fC/count ±3%; high range 400 fC/count ±5%.

Integral Linearity: Low range < ±(0.25% of reading + 2 counts); high range < ±0.50% of reading + 2 counts.

Differential Non-Linearity: ±30% typical, -0.75 LSB to +1.25 LSB maximum, see manual for details.

Operating Region: +10 mV to -1.5 V for specified linearity, (+0.2 mA to -30 mA into 50 ohm). (Guaranteed by design. Not tested.)

Noise: 0.8 counts R.M.S. typical, 2 counts maximum. Tested with no signals connected and a constant conver sion rate.

Interchannel Isolation: 75 dB typical, 60 dB minimum. (Guaranteed by design. Not tested.)

Temperature Coefficient: < ±(0.1% of reading + 1 count)/C (inputs unconnected or driven by a high impedance source). (Guaranteed by design. Not tested.)

Long Term Stability: ±(0.25% of reading + 1 count)/week. (Guaranteed by design. Not tested.)

Rate Effect: (Variation in pedestal with gate-clear repetition rate). Board average: 1.5 counts typical 2.5 counts max. Individual channel: board average ±1.5 counts. (Sample tested.)

Conversion Time: 265 µsec for all 96 channels. Subtract 2.7 µsec per channel if less than 96 channels are programmed for data taking.

Multiple Event Buffer: The digital data memory is large enough to store the results of up to eight events (8 times 96 A-to-D conversions). A 3-bit event counter allows the user to keep track of how many events the readout is trailing the A-to-D conversion.

Measure Pause Interval: 2 µsec to 300 µsec. (Guaranteed by design. Not tested.) Less than 2 µsec permitted, but a degradation of performance on channel 0 may occur.

Calibration Feature: Allows the gain of any channel to be measured to within ±1.5%. Needs an external DC voltage and a Gate signal. The charge pulse applied to all channels is proportional to the DC voltage across the differential Test Level Inputs on the FASTBUS backplane.

Voltage Range: 0 to 10 V. The calibration coefficient is 160pC/V.

Packaging: Single-width FASTBUS module (ANSI/IEEE 960-1986).

Power Requirements: 600 mA at +15 V; 3.1 A at +5 V; 400 mA at -2 V; 2.1 A at -5.2 V; 100 mA at -15 V (37.7 W total).

FASTBUS CONTROL

Addressing Modes: Geographic, and Broadcast (cases 1, 3, 4, 7). Implemented Registers: CSR0, CSR1, DSR0 (FIFO).

Module Identification Code: (1045)h.

Slave Status Responses to Data Cycles:

SS Significance

0 = Valid Action
1 = Busy
2 = End of Data
6 = Error. Invalid Mode
7 = Error. Invalid Secondary Address loaded into internal address register.

Implemented Broadcast Functions:

Code Significance Comments

01h* - General Broadcast Select: The ADC modules are selected and respond to subsequent data cycles.

09h - Sparse Data Scan: ADC modules containing data assert the T pin on the following read data cycle.

09h - Pattern Select: ADCs, seeing their T pin asserted on the following write data cycle, become selected to respond to subsequent data cycle.

0Dh - All Device Scan: All ADC modules assert their T pin on the following read data cycle.

9Dh - ADC SDS: Unique Sparse Data Scan for 1880 Series modules only. Follows standard SDS (see above).

CDh - Personality Card SDS: Sparse Data Scan: ADC asserts T pin if Personality Card requires service.

An h subscript indicates hexadecimal (base 16).

FASTBUS REGISTER CONFIGURATIONS

CSR 0 Write Bit Definitions

CSR 0 Read Bit Definitions

ID

After Power up or Reset
CSR 0 = 1045 3300

CSR 1 Bit Definitions

DSR 0 Output Data Word Bit Definitions

I - bits which give module ID upon read but are also implemented for write operations.

i - bits which give module ID upon read and are not used for write operations.

* - unused bits which read back zero.

R - bits implemented for read operations only.

W - bits implemented for write operations only.

X - bits implemented for read and write operations.

Auxiliary Connector
(Auxiliary Functions Card Socket)

Auxiliary Connector Pin
Allocations for the 1885F

Auxiliary Connector Pin Out Description

ISUMj: 1/10 of the sum of the ungated input currents of four adjacent channels (0 + 1 + 2 + 3), (4 + 5 + 6 + 7), .... (92 + 93 + 94 + 95). 0 j 23.

CLEAR, CLEAR*: ECL Fast Clear. Active from 20nsec after the time of application of the Fast Clear pulse at the CAT until 20 nsec after the next Gate Pulse.

GATE, GATE*: Differential ECL Conversion Gate Pulse. Occurs 20 nsec after the Gate is applied to the CAT. Duration equal to the input pulse.

R*/W: Defines direction of data bus.

WR-STR: Write strobe. Applied when the user writes to the CSR user space C0000000 h C0000015h.

A: 4-bit CSR user space address; e.g., CSR address C0000001 h corresponds to A = 1.

D: 8-bit data word.

NA (not available): TTL low level applied to pin A38 from the Auxiliary Card indicates that the CSR register accessed is implemented.

PCSTR: Personality Card Strobe, TTL level, active high.

PCT: Personality Card Trigger, TTL level, active low.

Copyright© January 1996. LeCroy is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publicaction supersedes all earlier versions.