GENERAL	2323A	4222
Packaging	Double-width CAMAC	Single-width CAMAC
START Input	-3 V to +3 V	-1.5 V to +1.5 V
STOP Input	NIM	NIM (Clear Input)
GATE WIDTH
Range	100 nsec to 10 sec or Latch Mode	170 nsec to 16.777215 msec
Jitter	< 0.3% of setting	150 psec R.M.S. max.
Accuracy	±0.2% of full scale	±200 psec ±time base error
Resolution	0.1% of full scale	1 nsec
Input to Output Delay	24 nsec	170 nsec typical
DELAYED OUT
Width	10, 30, 100 or 300 nsec	Latched until reset by CLEAR or next trigger if retrigger mode is selected
Occurs	Trailing edge of gate pulse	At end of delay
Rise Time	2 nsec max	1 nsec
Signal	NIM (-16 mA)	OUT: Standard negative NIM at end of delay. OUT*: Complement of OUT.
Miscellaneous	Ñ	Delay setting programmable from 170 nsec to 16.777215 msec
ADDITIONAL INPUTS AND OUTPUTS
Delayed Pulse	TTL/ECL	P1 - P4. Each Channel PULSE OUT delivers a 1 nsec rise time 5 V pulse (into 50 ½W) when the corresponding time delay has elapsed; pulse width 150 nsec ±10%.
BUSY	Ñ	NIM BUSY output state goes true in response to a valid Trigger and remains true until the end of the shortest delay or the end of the longest delay as seen by an internal switch.
OR	NIM OR'd with gate	Ñ
BLANK	NIM vetos gate	Ñ
POWER
24 V	+50 mA/-75 mA	+40 mA/-130 mA
12 V	Ñ	Ñ
6 V	+1.8 A/-1.3 A	+1.3 A/-2.5 A
	21.6 W	26.9 W
*Taken from +12 V if +6 V unavailable.