MTD135 Pin Descriptions
       

Acquisition

        

ACLK,ACLK*

 1,68 pECL Acquisition Clock  

COM,COM*

 6,7 pECL Common Hit Input  
       

I0*-I7*

 44,46,48, ... 58 CMOS Channel Input 0 through 7 (inverted)  

WE

 62 CMOS Write Enable, accept data  

TEST

 64 CMOS Test Input  

TE

 63 CMOS Test Enable, accept data from test input  
       

Configuration

        

MODE

 39 CMOS Mode select: Common Start/Stop  

LD/CLR

 8 CMOS Latch Threshold & Depth Data; clear data  

PE

 66 CMOS Positive Edge (leading) Enable  

NE

 65 CMOS Negative Edge (trailing) Enable  

DP3-DP0

 14,13,12,11 CMOS LIFO Depth Control  

T15-T4

 26-15 CMOS Threshold  
       

Control

        

DCN, DCP

 2,5   Delay Control, Negative/Positive Edges  

DN, DP

 3,4   Delay out, Negative/Positive  

ROSC

 40 CMOS Ring Oscillator (test device)  

ROE

 41 CMOS Ring Oscillator Enable  
       

Readout

        

RESET

 67 CMOS Clear time base counter  

PIN*

 36 CMOS Priority In, Enable Readout  

POUT*

 37 CMOS Priority Out, Readout Complete  

ACTIVE

 30 CMOS Readout Data Asserted  

RCLK*

 29 CMOS Readout Clock  

C0,C1,C2

 31,32,33 CMOS Channel Number  

H0, H1

 34,35 CMOS Hit Counter for Channel  

PHASE

 38 CMOS Edge Type Pos/Neg  

D0-D15

 11, 12, 13, ... 26 CMOS Time Measurements  
       

Power

        

Vdd (+5)

 9,27,42,47,51,55,59,61      

Vss (Gnd)

 10,28,43,45,49,53,57,60