LeCroy Voyager USB 3.0 Protocol Verification System

A comprehensive exerciser capability with support for both USB 2.0 and 3.0 traffic generation is built in to the Voyager M3 platform. The exerciser option allows users to transmit custom packets over standard USB cables with low-level control of headers, payloads, timing, and link states. The Exerciser is seamlessly integrated with the Protocol Analyzer, making the Voyager a complete test and development solution for engineers validating USB protocol.

ReadyLink is a full function link layer emulation mode built in to the exerciser. It automatically handles all USB 3.0 link training and link flow control to make development of test scenarios fast and easy. SuperSpeed USB devices require a nearly constant stream of low latency responses to manage flow control and link status. By including a complete link layer implementation resident in the exerciser hardware, the emulator operates at full line rate and correctly responds to the DUT as defined by the specification. ReadyLink alleviates the user from the nearly impossible task of manually scripting link layer responses.

Automating link layer responses is essential for providing comprehensive test coverage. It allows validation teams to use the exerciser for bring-up testing or directing the DUT to any logical link state.

By default, the ReadyLink emulation mode will automatically manage:

• Header Packet Acknowledgements (L_GOOD_n)
• Buffer Credit (L_CRD_x)
• SKIPs at required intervals (SKP)
• Link Synchronization
  • Responds to LFPS (Polling.LFPS)
  • Responds to polling sequence (Polling.RxEQ)
  • Responds to TS1 / TS2 handshaking sequence
• Power Management Link Commands
  • Responds to LGO_Un (with LAU)
  • Responds to LAU (with LMPA)

The ReadyLink emulation can be customized per test script to include various error scenarios, such as header LBADs and invalid link commands. Other errors include:

• 8B10B / CRC Error
• Running Disparity Error
• Corrupt Link Commands
• Corrupt Flow Control (Wrong L_CRD_x, Wrong L_GOOD_n, Drop L_Good_n, etc…)
• Corrupt Header Packet acknowledgement (Send LBAD, LRTY)
• Corrupt Packet Framing (SHP, SDP, END)

At the packet level, users have the freedom to send customized data payloads anywhere within the stream to verify protocol behavior. This makes it easy to insert logic errors, perform corner-case, or stress testing.

Special commands allow link layer error injection anywhere within the script

The Voyager Exerciser includes a text-based scripting interface; but any text editor can be used to create packet level traffic files. For USB 3.0 applications, test scenarios can contain multi-stage traffic generation blocks that include Boolean expressions such as LOOP, DO-CASE, and IF-THEN logical branching. Intelligent script pre-processor allows users to efficiently organize script code and create reusable generation blocks.

A library of predefined test scenarios including source code is provided allowing developers to adapt this substantial test suite to their own specific applications. Users can also create test scenarios by exporting any traffic stream from a previously recorded trace. These stimulus files can be played back bit-for-bit using LeCroy’s Exerciser mode. This allows validation engineers to easily recreate problems reported in the field or test specific functionality using a simple trace file.

The Exerciser editor includes pop-up shortcuts for common commands

The Voyager 2.0 exerciser is based on LeCroy’s legendary USBTrainer exerciser and is backward compatible with existing USBTrainer 2.0 traffic generation scripts. Capable of transmitting low, full, or high-speed traffic, the Voyager 2.0 exerciser also supports both host and device emulation.

For USB 2.0 applications, the Voyager exerciser supports both bitstream mode or Intelliframe mode which adds automatic wait states to the traffic stream. When enabled, the Intelliframe mode will intelligently wait for the appropriate response from the DUT before transmitting the next packet. For example, after issuing an IN, the generator waits for the DATAx packet returned by the device to finish, and then issues an ACK. When NAKs are received the Exerciser can automatically resend the previous packet. Used in conjunction with the Voyager analyzer, makes the LeCroy system the most flexible platform for USB development and compliance verification.

The Voyager M3 USB 3.0 Analyzer can support slower than standard clock rates. This option allows users to select clock rates at fractional intervals between 5Ghz and 1Mhz. This option also enables use of external clock sources to synchronize frequency of the Voyager system.

The external clock input is 3.3 volt LVPECL and operates on the USB 3.0 differential signals only. Device setup should be AC coupled at the clock input with a 10 uF ceramic capacitor. When enabled - the slow clock option affects both the analyser (record) and the exerciser (transmit) frequencies.

LeCroy’s Voyager M3 platform for USB 3.0 includes an optional SMA Differential Input tapping mechanism for probing SuperSpeed Links. The SMA Input can serve as an alternate interface for taping between early development boards. This eliminates dependencies on USB 3.0 connectors allowing testing to begin as soon as PHY silicon is available. This also allows test teams to remove an additional variable (prototype 3.0 connectors) from the test matrix to help isolate protocol layer issues from possible physical layer problems.

The optional SMA Differential Input can be utilized on host, device or both sides of the SuperSpeed link. It will operate with the analyzer in record mode or can be used with the exerciser additionally to allow transmit and record over this alternate cabling interface.

LeCroy’s Voyager USB 3.0 system provides a unique capability to import comma separated value (.CSV) text files into the CATC trace display. This option is intended for engineers performing pre-silicon verification using Verilog, VHDL, and C++ based development environments. These software-based environments are commonly used to synthesize ASIC and FPGA based prototype hardware.

The use of EDA tools to perform functional verification of SuperSpeed protocol helps users find and fix problems before committing a design to silicon. These verification packages generate USB compliant test vectors which run against RTL or VHDL simulations. The output of these test suites can be imported into the Voyager USB 3.0 software. These simulations will be displayed using the CATC Trace with both host and device traffic clearly marked and time-stamped.

Traffic appears as though it was recorded using the analyzer with full search and decoding capability. This makes it a valuable debugging tool for analyzing and understanding functional verification output.